ARRIS-D5-QAM-POST-MIB

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Organization: Arris International

Last Updated: 2009-09-09

Description: Manufacturing Power-On Self-Test (POST) diagnostics MIB for ARRIS D5 Universal Edge QAM, tracking memory and hardware test results

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What Is ARRIS-D5-QAM-POST-MIB?

ARRIS-D5-QAM-POST-MIB is an ARRIS manufacturing/diagnostics MIB for the D5 Universal Edge QAM (UEQAM) platform, used to record Power-On Self-Test (POST) results during manufacturing and hardware bring-up. It exposes pass/fail style test results for memory and other hardware subsystems exercised during the device's self-test sequence. This is a hardware-status MIB in the narrowest sense: it captures one-time or boot-time diagnostic outcomes (e.g., memory test pass/fail) rather than continuous runtime performance counters, so it is more relevant to factory test and initial hardware qualification than to ongoing operational monitoring. It is specific to ARRIS's D5 UEQAM manufacturing tooling with no notable dependency on external standard MIBs. It is used in ARRIS factory/manufacturing test environments and potentially field diagnostics for D5 Universal Edge QAM devices deployed in cable head-ends. Engineers can download the ARRIS-D5-QAM-POST-MIB file directly to load it into their MIB browser.

IPNetwork Monitor allows you to monitor SNMP objects defined in ARRIS-D5-QAM-POST-MIB. Use the built-in SNMP Monitoring Browser to explore available variables, view their current values and descriptions, and select the objects you want to monitor. You can then create SNMP monitors, configure thresholds, and receive alerts when monitored values change.

Supported Devices

ARRIS D5 Universal Edge QAM (UEQAM)

Monitoring Examples

Because sample_objects is empty for this entry, exact object names cannot be confirmed, but the module's purpose implies POST result objects for memory subsystems and other hardware blocks that report a pass/fail or error-code status after each boot-time self-test on a D5 UEQAM card. A technician would check these results after manufacture or after a suspected hardware fault to confirm memory and hardware POST completed successfully before the unit is deployed to a cable head-end.

What Can Be Monitored

memory POST pass/fail result
hardware self-test result codes

Imported Objects

From ARRIS-D5-QAM-MIB

d5QamMib

MODULE-IDENTITY

From ARRIS-D5-VIDEO-MIB

D5Program

From ARRIS-MIB

arrisD5UEQam

OBJECT-IDENTITY

From DOCS-IF-MIB

TenthdBmV

From ENTITY-MIB

PhysicalIndex

From IF-MIB

InterfaceIndex
ifIndex	OBJECT-TYPE

From SNMPv2-CONF

MODULE-COMPLIANCE
OBJECT-GROUP

From SNMPv2-SMI

Counter32
Integer32
MODULE-IDENTITY
OBJECT-TYPE
Unsigned32

From SNMPv2-TC

DisplayString
RowStatus
TruthValue

OIDs

OID symbolic	OID numeric	Type	Access	Description
d5QamPOSTMib	1.3.6.1.4.1.4115.1.8.1.5.2			Arris D5 UEQ QAM Manufacturing MIB
d5QamMemoryTestTable	1.3.6.1.4.1.4115.1.8.1.5.2.1		not-accessible	This table contains a list of QAM POST tests and test-results for each of the memory banks
d5QamMemoryTestEntry	1.3.6.1.4.1.4115.1.8.1.5.2.1.1		not-accessible	An entry for a single memory bank POST test and result.
U32 d5QamMemoryTestSlotId	1.3.6.1.4.1.4115.1.8.1.5.2.1.1.1	Unsigned32	not-accessible	QAM card associated with a particular test.
U32 d5QamMemoryTestBankId	1.3.6.1.4.1.4115.1.8.1.5.2.1.1.2	Unsigned32	not-accessible	A unique identifier specifying a particular memory bank.
STR d5QamMemoryTestDescription	1.3.6.1.4.1.4115.1.8.1.5.2.1.1.3	DisplayString	read-only	A textual description of the the memory bank.
INT d5QamMemoryTestChip	1.3.6.1.4.1.4115.1.8.1.5.2.1.1.4	INTEGER	read-write	Select a particular chip for a DVT test, this field is ignored for all other tests
INT d5QamMemoryTestExecute	1.3.6.1.4.1.4115.1.8.1.5.2.1.1.5	INTEGER	read-write	Control for starting a test and checking for test completion. Only a value of stop or startXXX is allowed on write access. Only a value of idle or running is allowed on read access.
U32 d5QamMemoryTestResultVector	1.3.6.1.4.1.4115.1.8.1.5.2.1.1.6	Unsigned32	read-only	Last test result vector, its interpretation is test specific
U32 d5QamMemoryTestResultRegister	1.3.6.1.4.1.4115.1.8.1.5.2.1.1.7	Unsigned32	read-only	Last test result register, its interpretation is test specific
U32 d5QamMemoryTestResultAddress	1.3.6.1.4.1.4115.1.8.1.5.2.1.1.8	Unsigned32	read-only	Last test result address, its interpretation is test specific
d5QamRS232Table	1.3.6.1.4.1.4115.1.8.1.5.2.2		not-accessible	This table allow access to RS232 bus of available QAM cards
d5QamRS232Entry	1.3.6.1.4.1.4115.1.8.1.5.2.2.1		not-accessible	An entry for a single QAM card RS232 bus.
U32 d5QamRS232SlotId	1.3.6.1.4.1.4115.1.8.1.5.2.2.1.1	Unsigned32	not-accessible	Slot associated with a particular QAM card.
U32 d5QamRS232Status	1.3.6.1.4.1.4115.1.8.1.5.2.2.1.2	Unsigned32	read-only	Retrieve the status of the RS232 bus as documented in D5 Mux & PHY FPGAs Firmware Interface Specification section [2.4.14]
OCT d5QamRS232Data	1.3.6.1.4.1.4115.1.8.1.5.2.2.1.3	OCTET STRING	read-write	On writing, the octet string is pushed to the RS232 transmit FIFO and flushed to the QAM micro-controller. On reading, the octet string contains the content of the RS232 receive FIFO.
d5QamECLTable	1.3.6.1.4.1.4115.1.8.1.5.2.3		not-accessible	This table allow access to ECL bus of available QAM cards
d5QamECLEntry	1.3.6.1.4.1.4115.1.8.1.5.2.3.1		not-accessible	An entry for a single QAM card ECL bus.
U32 d5QamECLSlotId	1.3.6.1.4.1.4115.1.8.1.5.2.3.1.1	Unsigned32	not-accessible	Slot associated with a particular QAM card.
U32 d5QamECLAddress	1.3.6.1.4.1.4115.1.8.1.5.2.3.1.2	Unsigned32	read-write	the ECL address for the transaction
U32 d5QamECLValue	1.3.6.1.4.1.4115.1.8.1.5.2.3.1.3	Unsigned32	read-write	The ECL value for the write transaction, or the result of a Read transaction.
INT d5QamECLExecute	1.3.6.1.4.1.4115.1.8.1.5.2.3.1.4	INTEGER	read-write	Control for an ECL transaction. Only a value of read or write is allowed on write access. Only a value of idle, running or fail is allowed on read access.
d5QamConfigurationControlTable	1.3.6.1.4.1.4115.1.8.1.5.2.4		not-accessible	This table allow controlling internal aspects of QAM card configuration
d5QamConfigurationControlEntry	1.3.6.1.4.1.4115.1.8.1.5.2.4.1		not-accessible	An entry for a single QAM card configuration.
U32 d5QamConfigurationControlSlotId	1.3.6.1.4.1.4115.1.8.1.5.2.4.1.1	Unsigned32	not-accessible	Slot associated with a particular QAM card.
T/F d5QamConfigurationControlResetNow	1.3.6.1.4.1.4115.1.8.1.5.2.4.1.2	TruthValue	read-write	Setting this object to true(1) causes the device to reset. Reading this object always returns false(2).
T/F d5QamConfigurationControlManufacturingTests	1.3.6.1.4.1.4115.1.8.1.5.2.4.1.3	TruthValue	read-write	Enable/disable manufacturing tests.
T/F d5QamConfigurationControlPreDistortionCoefs	1.3.6.1.4.1.4115.1.8.1.5.2.4.1.4	TruthValue	read-write	Enable/disable pre-distortion coefficients usage.
d5QamPOSTConformance	1.3.6.1.4.1.4115.1.8.1.5.2.99
d5QamPOSTGroups	1.3.6.1.4.1.4115.1.8.1.5.2.99.1
d5QamPOSTGroup	1.3.6.1.4.1.4115.1.8.1.5.2.99.1.1			Description.
d5QamPOSTCompliances	1.3.6.1.4.1.4115.1.8.1.5.2.99.2
d5QamPOSTCompliance	1.3.6.1.4.1.4115.1.8.1.5.2.99.2.1			Description.

RFC description

Manufacturing POST tests for QAM memory banks on Arris D5 UEQ hardware.

Start monitoring ARRIS D5 Universal Edge QAM (UEQ) (legacy) with a free 30-day trial of IPNetwork Monitor. Import MIBs, browse SNMP OIDs, create custom SNMP monitors, configure alerts, and monitor any SNMP-enabled network device from a single console.

Download ARRIS-D5-QAM-POST-MIB

What Is ARRIS-D5-QAM-POST-MIB?

Supported Devices

Monitoring Examples

What Can Be Monitored

This MIB depends on

Related MIBs

RFC description