This read-write value sets the maximum cell arrival jitter, in microseconds, that the channel's reassembly process will tolerate before treating arriving cells as too delayed, with card-specific ceilings such as 24 milliseconds for T1 and only 1.447 milliseconds for T3. An administrator raises this value on links with more jitter (such as those crossing more network hops) to avoid unnecessary buffer underflows, while keeping it as low as practical to minimize the added latency from buffering. For example, the default of 1000 microseconds for T1/E1 channels may need to be increased on a particularly jittery path, while T3 channels are constrained to a much tighter maximum given the tighter delay budget of that circuit type.