All MIBs › CIENA-CES-DATAPLANE-MIB › cienaCesDpCpuSubInterfaceEgressL2Transform
cienaCesDpCpuSubInterfaceEgressL2Transform
Module: CIENA-CES-DATAPLANE-MIB
OID (symbolic): CIENA-CES-DATAPLANE-MIB::cienaCesDpCpuSubInterfaceEgressL2Transform
OID (numeric): 1.3.6.1.4.1.1271.2.1.7.1.12.1.1.3
Node type: OBJECT-TYPE
Type: OCTET STRING
Access: read-only
Description: This object specifies the egress L2 transform for this CPU sub-interface.
Format: push-ethtype.vid.pcp
What is cienaCesDpCpuSubInterfaceEgressL2Transform?
Encodes, in the documented 'push-ethtype.vid.pcp' format, the Layer 2 header transform (an Ethertype push plus VLAN ID and priority bits) applied to frames as they leave this CPU sub-interface. Since this is how the switch tags control-plane frames destined for the CPU with the right VLAN/priority before they're handed off, a mismatch here would show up as CPU-bound traffic (like DHCP relay responses) arriving on the wrong VLAN or losing its priority marking. A typical value might decode to pushing Ethertype 0x8100 with VID 4093 and PCP 7, tagging CPU traffic into a dedicated high-priority management VLAN.
Examples
Walk all instances (SNMPv2c):
snmpwalk -v2c -c public <target> 1.3.6.1.4.1.1271.2.1.7.1.12.1.1.3 snmpwalk -v2c -c public <target> CIENA-CES-DATAPLANE-MIB::cienaCesDpCpuSubInterfaceEgressL2Transform
Get a specific instance (index 1):
snmpget -v2c -c public <target> 1.3.6.1.4.1.1271.2.1.7.1.12.1.1.3.1 snmpget -v2c -c public <target> CIENA-CES-DATAPLANE-MIB::cienaCesDpCpuSubInterfaceEgressL2Transform.1
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OID Breakdown
Upper-level ancestors (9 from the standard OID tree / other modules)
| Numeric OID | Name | Module |
|---|---|---|
| 1 | iso | LANART-AGENT |
| 1.3 | org | AirPair-MIB |
| 1.3.6 | dod | AirPair-MIB |
| 1.3.6.1 | internet | AirPair-MIB |
| 1.3.6.1.4 | private | AirPair-MIB |
| 1.3.6.1.4.1 | enterprises | AirPair-MIB |
| 1.3.6.1.4.1.1271 | ciena | CIENA-SMI |
| 1.3.6.1.4.1.1271.2 | cienaCes | CIENA-SMI |
| 1.3.6.1.4.1.1271.2.1 | cienaCesConfig | CIENA-SMI |
| Numeric OID | Name | Module |
|---|---|---|
| 1.3.6.1.4.1.1271.2.1.7 | cienaCesDataplaneMIB | CIENA-CES-DATAPLANE-MIB |
| 1.3.6.1.4.1.1271.2.1.7.1 | cienaCesDpMIBObjects | CIENA-CES-DATAPLANE-MIB |
| 1.3.6.1.4.1.1271.2.1.7.1.12 | cienaCesDpCpuSubInterface | CIENA-CES-DATAPLANE-MIB |
| 1.3.6.1.4.1.1271.2.1.7.1.12.1 | cienaCesDpCpuSubInterfaceTable | CIENA-CES-DATAPLANE-MIB |
| 1.3.6.1.4.1.1271.2.1.7.1.12.1.1 | cienaCesDpCpuSubInterfaceEntry | CIENA-CES-DATAPLANE-MIB |
| 1.3.6.1.4.1.1271.2.1.7.1.12.1.1.3 | cienaCesDpCpuSubInterfaceEgressL2Transform | CIENA-CES-DATAPLANE-MIB |