All MIBs › ALCATEL-IND1-TIMETRA-PORT-MIB › tmnxBundleRedDiffDelay
tmnxBundleRedDiffDelay
Module: ALCATEL-IND1-TIMETRA-PORT-MIB
OID (symbolic): ALCATEL-IND1-TIMETRA-PORT-MIB::tmnxBundleRedDiffDelay
OID (numeric): 1.3.6.1.4.1.6527.3.1.2.2.4.14.1.11
Node type: OBJECT-TYPE
Type: Unsigned32
Access: read-create
Description:
tmnxBundleRedDiffDelay configures the maximum acceptable differential delay for individual circuits within this multilink bundle. If the delay exceeds this threshold, a tmnxEqPortBndlRedDiffExceeded trap is issued.
For a tmnxBundleType value of 'imagrp' a range of 0 to 50 is supported, 0 to 25 otherwise.
What is tmnxBundleRedDiffDelay?
Configures the red (critical) threshold for differential delay between individual circuits in a multilink bundle; if any circuit's delay exceeds this value, a tmnxEqPortBndlRedDiffExceeded trap is generated. For IMA group bundles, only the 'down' action is supported when this threshold is crossed.
OID Breakdown
| Numeric OID | Name | Module |
|---|---|---|
| 1 | iso | LANART-AGENT |
| 1.3 | org | BIANCA-BRICK-PPP-MIB |
| 1.3.6 | dod | BIANCA-BRICK-PPP-MIB |
| 1.3.6.1 | internet | BIANCA-BRICK-PPP-MIB |
| 1.3.6.1.4 | private | BIANCA-BRICK-PPP-MIB |
| 1.3.6.1.4.1 | enterprises | ANIROOT-MIB |
| 1.3.6.1.4.1.6527 | timetra | ALCATEL-IND1-TIMETRA-GLOBAL-MIB |
| 1.3.6.1.4.1.6527.3 | timetraProducts | ALCATEL-IND1-TIMETRA-GLOBAL-MIB |
| 1.3.6.1.4.1.6527.3.1 | tmnxSRMIB | ALCATEL-IND1-TIMETRA-GLOBAL-MIB |
| 1.3.6.1.4.1.6527.3.1.2 | tmnxSRObjs | ALCATEL-IND1-TIMETRA-GLOBAL-MIB |
| 1.3.6.1.4.1.6527.3.1.2.2 | tmnxHwObjs | ALCATEL-IND1-TIMETRA-CHASSIS-MIB |
| 1.3.6.1.4.1.6527.3.1.2.2.4 | tmnxPortObjs | ALCATEL-IND1-TIMETRA-PORT-MIB |
| 1.3.6.1.4.1.6527.3.1.2.2.4.14 | tmnxBundleTable | ALCATEL-IND1-TIMETRA-PORT-MIB |
| 1.3.6.1.4.1.6527.3.1.2.2.4.14.1 | tmnxBundleEntry | ALCATEL-IND1-TIMETRA-PORT-MIB |
| 1.3.6.1.4.1.6527.3.1.2.2.4.14.1.11 | tmnxBundleRedDiffDelay | ALCATEL-IND1-TIMETRA-PORT-MIB |