This read-write INTEGER, constrained to between 40,000,000 and 120,000,000 Hz, sets the targeted interconnect clock frequency that must be established before system operation begins. An administrator configures this alongside platformTargetProcClockMultiple and platformTargetJtagClockFreq as the guideline the platform uses to set up its actual clocks, with the values persisted in SSP storage. For example, setting this target too high for the installed processors could prevent the interconnect from reaching a stable operating frequency at boot.