This reports which specific bit position, Sa4 through Sa7, the spare bits defined in the E1 frame structure, this output uses to carry the SSM quality-level code to the downstream BITS receiver, since different equipment and regional standards can place SSM signaling in different Sa-bit locations. An admin whose downstream BITS receiver isn't correctly reading the advertised quality level despite the timing signal itself being locked should check whether this SSM location matches what the receiving equipment expects. For example, an output signaling SSM on the Sa4 bit while the downstream receiver is configured to read SSM from Sa7 would cause that receiver to see no valid quality information even though the underlying clock signal is fine.