This reports the state of the standby PLL that backs up the primary clock generator on this node. Since this PLL is the standby, its state matters most during a primary PLL failure: down(2) here at the same time the primary is down means the node has no working clock generator left and will free-run, risking bit slips on every T1 or E1 circuit it carries. For example, seeing both PLLs down(2) simultaneously would be the trigger to dispatch a field tech to replace the clock or timing module before circuits start slipping.