This counter tracks frames known to be lost because the internal receive FIFO overflowed -- also called a receive overrun -- which the MIB attributes to the device being unable to get necessary PCI bandwidth, noting the failure can cascade to subsequent frames if the overflow persists. Crucially, a frame counted here will NOT also be counted in the CRC-error, misalignment, or short-frame counters, so this counter isolates a distinct 'we simply couldn't keep up' failure mode from those signal-integrity failure modes. If this counter and the Tx DMA underrun counter both climb together during the same busy period, that pattern confirms the router's shared internal bus bandwidth, not the Ethernet cabling, is the bottleneck on both the Tx and Rx sides.