This is a bit-masked attribute which displays events which may cause HSB Reset. When a bit is '1', the relevant evet may cause HSB Reset. When a bit is '0', the relevant evet will not cause HSB Reset. The following are the events: LSB D0 - Too many packets were discarded from a queue. D1 - One of the Tx buffers to HSB is full for more than a default period. D2 - Token has not been available for more than a default period. D3 - RX Buffer full in one of the ports. D4 -'1' HSB Reset has been occured , '0'- HSB reset hadn't occured since last time this MIB has been read. D5 - '0' - the ram of the relevant port is O.K. (the port is decode in D6-D7) , '1' The ram is not O.K. D6- D7 Decode the relevant port that It's ram is not O.K 00 - Port no'0 01 - Port no' 1 10 - Port no' 2 11 - Port no' 3.